发明名称 BUS SYSTEM COMPENSATING DELAY AMOUNT
摘要 PURPOSE:To make the time reaching a main device coincident with each other, by making a slave device receiving a specific signal from a transmission, master device transmit a response signal with a delay by a time diference between the returned signal from own device and that from a slave device located at the farthest position. CONSTITUTION:A clock signal transmitted on an outgoing bus line 4 from a transmission master device 1 reaches a slave transmission device 2i. The arrived clock signal is transmitted to an incoming bus line 5 from a clock extracting device 14i via a phase comparator 13i. Further, the slave transmitter 2M located farthest from the slave device 2i transmits similarly the clock signal to the incoming bus line 5. The slave transmitter 2i receives the incoming return signal from the slave transmitter 2M and gives it to a phase comparator 13i. The phase comparator 3i detects the time difference between the clock signal from the received slave transmitter 2M and the clock signal returned by itself. The transmission circuit 12i returns the own clock signal with a delay by this time defference. Thus, the returned signals from each slave transmitter reach the master transmitter 1 at the same time.
申请公布号 JPS5962248(A) 申请公布日期 1984.04.09
申请号 JP19820173533 申请日期 1982.10.01
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 OKUMURA YASUYUKI;HAYASHI KAZUHIRO
分类号 H04L12/40 主分类号 H04L12/40
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