| 摘要 |
PURPOSE:To increase easily the capacity of transmission capacity, by miltiplexing n RZ low speed data array signals as one high-speed data array in a cyclic data transmitting system. CONSTITUTION:A receiving timing signal RT is reproduced from an RZ high- speed data array RZHD received from a line to reproduce a receiving high- speed data array by using said timing signal RT. A synchronous word is detected from the data array and the data array is synchronously protected by the prescribed number of times. A frequency dividing circuit 25 is synchronized in phase by a reset signal from a synchronous protecting circuit 24, a regular signal is inputted to a temporary storage circuit 29 and a nagative-phase signal is inputted to a temporary storage device 30. The receivied high-speed data array inputted from a data reproducing circuit 22 is held at its outputs during the period regulated by the positive and nagative phase signals, and AND circuit 31, 32 find out the ANDs of the data arrays respectively, so that AND is found by RZ and RZ low-speed data arrays RZLD1, RZLD2 are obtained to supply these data arrays to respective receiving parts 33, 34. |
