| 摘要 |
PURPOSE:To attain surely the synchronism by adjusting the phase with insertion or deletion of a pulse. CONSTITUTION:When the synchronism between an input signal AS and an output signal BS is shifted for a prescribed amount or over, a phase difference detecting circuit 2 generates a detecting signal ES. When the phase of the signal AS is advanced in comparison with the phase of the BS, a signal commanding an up-count is generated from a phase comparator 1 to an up-down counter 42. A data selector 43 reads out frequency information corresponding to a count value from a storage device 41 and applies it to a staff/destaff control circuit 51. The staff/destaff control circuit 51 performs staff/destaff to a high speed clock CKS to lock the signals AS and BS. Thus, even if momentary interruption takes place in the input signal, remarkable out of synchronism does not take place in the output signal. |
