| 摘要 |
PURPOSE:To prevent such a case that once accepted interruption processing remains interrupted by insuring an offering request from the outside against being reset after the processing of error, which may occur while a memory is read and written, is completed. CONSTITUTION:According to a micro instruction (a), data is initially read and written in the memory. Immediately after an offering request is issued from an external device, a CPU sets a flip-flop 9. Afterwards, the instruction advances, a signal 100 comes to a high level at the timing of a mu-END (microend of the micro-instruction), and a clock to the CPU from a basic clock generator circuit 14 is interrupted by a gate 15. Accordingly, even if error processing is executed in the middle of memory read/write execution, the flip-flop 9 is not reset, and the interruption request from the external device can be surely executed at the initial mu-END after error processing ends.
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