| 摘要 |
PURPOSE:To widen the range of the linearity by connecting the gate of the 3rd FET to drains of two FETs and connecting the drain of the 4th FET to the source of the 3rd FET so as to decrease the effect of the on-resistance of a switch to negligibly small value due to a signal level. CONSTITUTION:Each drain of FETs 7, 8 is connected to the gate of a FET 11, the drains is connected to a voltage source VDD 9 and the source is connected to an output terminal 5. The source and gate of the FET 12 are connected to a voltage source VSS 10, its drain is connected to the output terminal 5 and the output terminal 5 is connected to ground via a load resistor 6. The output of the FET switch 7 or 8 is received by the gate of the FET and a signal is delivered to an output load resistor via a source follower circuit. Thus, the output of the FET switch 7 or 8 is hardly effected by the change in the switch on-resistance due to the signal level change. Further, as the input/output characteristic of the source follower circuit, the characteristic with excellent linearity is obtained by selecting properly the input level of the source follower and the power supply voltages VDD, VSS.
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