发明名称 SYSTEM FOR INHIBITING EXTRACTION OF INSTRUCTION AND CANCELLIG INHIBITION IN INFORMATION PROCESSOR
摘要 PURPOSE:To improve the performance, by performing the inhibition and cancellation of the inhibition of extraction of an instruction based on a readout data of control storage so as to attain freely the inhibiting and the cancellation of the inibition of an unnecessary instruction. CONSTITUTION:An instruction is read out from a storage device 1, stored in an instruction buffer register 2 or 4 and given to a pipeline control section 6 through a selectors 5. Then, the information of the control storage CS10 is read out on a phase A tag 8 and when its specific bit is ''1'', a latch circuit FF9 is set to ''1'', and when ''0'', it is sent to ''0''. An instruction control section 7 inhibits the extraction of instruction when the circuit 9 is set to ''1'', and the inhibition of instruction extraction is cancelled when the circuit 9 is set to ''0''. Thus, the inhibition of advance-fetch and the cancellation of the inhibition of the unnecessary instruction are performed freely during the execution of the instruction or in the instruction.
申请公布号 JPS5957348(A) 申请公布日期 1984.04.02
申请号 JP19820146915 申请日期 1982.08.26
申请人 FUJITSU KK 发明人 MIZUSHIMA YOSHIHIRO;SATOU KIYOSUMI
分类号 G06F9/38;(IPC1-7):06F9/38 主分类号 G06F9/38
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