| 摘要 |
PURPOSE:To prevent lowering of processing speed without requiring extension of an internal circuit of a processor by dividing a real space for each interruption level of the processor and accessing alloted part of the real space through an imaginary space. CONSTITUTION:It is supposed that a processor 1 is operating at an interruption level (n) and the access to a storage device system 5 is started. An interruption level signal (n) is supplied to a changeover device 4, and a part Mn of a real space alloted to the interruption level (n) is made accessible through an imaginary space 3. Programs, data etc. of interruption level (n) are stored in the real space 5. Such a process is generated by all interruption level, and the capacity of an access bus required for access is the same throughout all accesses. |
