| 摘要 |
PURPOSE:To attain a semiconductor memory which can be always operated in a high speed independently of the variance of every production lot, the variation of temperature, etc., by incorporating a dummy cell including practically the same constitution as a memory cell in a bit line selecting circuit to compensate the variation of the current and voltage characteristics of the memory cell. CONSTITUTION:A memory cell MC is connected at the intersection between a pair of word lines W+ and W- and a pair of bit lines BL and -BL. The word line W+ is connected to a word driver T4; and when this word line W+ is selected by the output of a word decoder, it is set to the H level. A pair of bit lines BL and -BL are selected through a bit line switching circuit BSW, and this circuit consists of transistors TRs T1 and T2. A dummy cell is incorporated in a bit selecting circuit BSL1; and if a voltage VBL which appears on bit lines from the word line W+ through the memory cell MC is varied to a higher or lower value by the variance of production lots, the variations of temperature, etc., a similar variation is generated by the dummy cell DC, and thus, an apparent bias voltage VBC is invariable. |
