发明名称 CPU CONTROL SYSTEM
摘要 PURPOSE:To track an error, by latching previously an address signal and a strobe signal which are fed to a memory device from a CPU, then reading out the latched signal by an interruption signal when a ready signal is not fed back within a specified time. CONSTITUTION:An address signal and a strobe signal of R/W are sent to a memory device 8 from a CPU1, and at the same time the data is latched 2 previously. When no ready signal is fed back within a fixed time, a monostable multivibrator 7 has a reverse operation. Then an interruption signal INT is fed to the CPU1 from a controller 6 by an output TO. The CPU1 uses a decoder 3 to open a gate 4 and reads the contents held at the latch 2 to obtain an address data that causes an error. Thus it is possible to trace the error.
申请公布号 JPS5955551(A) 申请公布日期 1984.03.30
申请号 JP19820165787 申请日期 1982.09.22
申请人 RICOH KK 发明人 YAMADA HIROSADA
分类号 G06F11/34;(IPC1-7):06F11/34 主分类号 G06F11/34
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