| 摘要 |
PURPOSE:To attain a high-speed operation, by connecting in common the sources of two depletion type FETs each of which connects its gate directly to its source and connecting the sources connected in common to the input of a depletion type inverter circuit. CONSTITUTION:Each of the depletion type FETs 51, 52 connects its gate directly to its source and the sources of the FETs 51, 52 are connected in common to the input 57 of the depletion type inverter circuit 53. The drains 54, 55 of respective FETs 51, 52 are used as respective input terminals and the output of the circuit 53 is used as an output terminal to constitute a two-input gate circuit. If the current amplification factors of the FETs 51, 52 are set up uniformly and each threshold voltage is -2.5V in said constitution, 0.8V is obtained at the input level 57. Since the 0.8V is recognized as 0 on the + side, the circuit configuration operates equivalently to a two input NAND gate circuit using the drains 54, 55 as the input terminals and the output 56 as the output terminal. Consequently, a high-speed operation is attained. |
