| 摘要 |
PURPOSE:To discontinue the working of a signal processor and therefore to decrease the power consumption of a digital signal control circuit, by stopping the supply of an internal clock to a digital signal processor until the next sampling signal period after the digital signal is processed. CONSTITUTION:A synchronizing signal presets a flip-flop (FF) circuit 10 via a differentiating circuit 17, and level ''1'' is supplied to an AND gate 7 from the circuit 10. At the same time, a clock 3 delivered from a clock pulse generator 6 is supplied to a digital signal processing circuit 5. While, the sampling data is supplied to the circuit 5 and processed digitally by a prescribed program. When the processing is through with the digital signal at the circuit 5, an end signal is delivered through a terminal 8. This end signal is supplied to an input terminal 11 of the circuit 10 as well as to an input terminal 13 of the circuit 10 via an inverter 12. Therefore the terminal Q of the circuit 10 is set at level ''0'', and the clock 3 is stopped by the gate 7. |
