| 摘要 |
The arrangement contains two transistors (T1, T2) which are alternately conducting in such a manner that the second transistor (T2) conducts whenever a logic "0" is present at the input (E) and thus at the base of the first transistor (T1). If the second transistor (T2) is conducting, a charge passes via it from a current source (S) to a capacitor (C) which can slowly discharge again via a resistor (R1). A voltage which indicates an AIS signal below a predetermined value builds up across the capacitor (C) in accordance with the frequency of occurrence of bits with the logic state "0". <IMAGE>
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