| 摘要 |
A standard chip for operating a cyclically operating buffer store (PUF) with address-controlled access optionally as transmitting and/or receiving buffer at the ends of a data or information transmission link. Apart from the address registers (REG-S, REG-L) for the read and write pointer (L and S), two or only one further register (for example REG-F, REG-W) are provided for deriving a release pointer (F) for identifying the next storage location to be released for the read-out and for deriving a repeat pointer (W) for identifying the next storage location to be selected for repeated reading. All registers control the buffer store (PUF) as pointer control (ZST) in connection with a logic arrangement (VL) and in dependence on differentiated control instructions (OP) from a higher-level sequence control (ABL-ST), determining the operation of the buffer store (PUF), in which arrangement the pointers, compared pair by pair, are used for checking the executability of the control instruction provided in each case, this instruction is executed or rejected while simultaneously changing the pointers and the type of instruction response is identified by an acknowledgement (RO/1). A multiplicity of variants for constructing the logic arrangement (VL). Asynchronous operation of two separate sequence controls in conjunction with the logic arrangement as standard chip in conjunction with an access control is also possible. <IMAGE> |
