发明名称 |
TIMING DELAY EQUALIZATION CIRCUIT |
摘要 |
A circuit for generating a common signal as a function of either of two reference signals comprises a pair of phase-locked loops which share an oscillator. Each phase-locked loop generates a control signal as a function of one of the reference signals. One or the other of the control signals is coupled to the oscillator which generates the common signal. A comparator compares the two control signals and generates a signal indicative of their difference. While the control signal generated by the first phase-locked loop is coupled to the oscillator, the difference signal is applied to the second phase-locked loop where it controls the generation of the second control signal to minimize the difference between the two control signals. While the control signal generated by the second phase-locked loop is coupled to the oscillator, the second phase-locked loop is nonresponsive to the difference signal. Thus when a switch of reference signals occurs even if they are of different phase and even if that phase is slowly time-varying, the circuit can lock to the new reference signal at a phase dictated by the phase difference between the two references at the instant of the switch without causing the oscillator output to undergo significant frequency or phase changes. |
申请公布号 |
AU1479983(A) |
申请公布日期 |
1984.03.29 |
申请号 |
AU19830014799 |
申请日期 |
1983.03.25 |
申请人 |
WESTERN ELECTRIC COMPANY, INC. |
发明人 |
DOMBROWSKI, LEONARD CHESTER |
分类号 |
H03L7/087;H03L7/14;H04J3/06;H04L1/22;H04L7/00;H04L7/033;H04Q11/04 |
主分类号 |
H03L7/087 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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