| 摘要 |
PURPOSE:To enable to increase the delay time without introducing the increase in the pattern area by forming a wiring part from the gate of an MOS transistor to a gate terminal of a high resistance layer. CONSTITUTION:Gates of a P-MOS delay transistor QPR and N-MOS delay transistor QNR are commonly connected, and connected at the output side to a capacitor C. When an input VIN varies from VSS to VDD at a time t0, the variation in the input VIN is transmitted to a high resistance layer, and a voltage V2 which is presented on the gate layer gradually increases. The falling delay time DELTAtauf to the rising input and the rising delay time DELTAtaur to the falling input can be all varied by the resistance Rg of the high resistance layer and the static capacitance Cg of the gate layer, and also by the threshold voltages VTN, VTP. |
