| 摘要 |
The invention relates to a decoder circuit which comprises a number of NOR decoder gates (G1). The latter can be selected via address lines (L1 ... L2n). The object is to attain a reduction in power consumption compared with conventional circuits of this type. This is achieved according to the invention by inserting a switching transistor (TS1) in the branch (2) of each NOR decoder gate (G1) to which the supply voltage is applied, which transistor is activated via an address line (L4) which is not used to activate the other switching transistors (T1 ... Tn) of the same gate (G1). No shunt current therefore occurs on around half of all unselected gates. The field of application includes integrated MOS logic circuits.
<IMAGE>
|
