| 摘要 |
PURPOSE:To reduce a quantity of hardware, and to shorten an arithmetic executing time, by executing a double precision adjustment to a high rank side data value and a low rank side data value of a double precision data. CONSTITUTION:An input data value #1 of an input signal 11 and an input data value #2 display an absolute value with a code, by a code 14 and an absolute value 12, and a code 15 and an absolute value 13, respectively. In case when a value of a single precision/double precision arithmetic switching signal 16 is ''0'', when a value of an addition/subtraction designating signal 17 is ''0'', ''1'', addition and subtraction are executed, respectively, between the input signal #1 and #2, and an output signal 19 is generated. When the switching signal 16 is ''1'', subtraction is executed irrespective of a value of the signal 17. Subsequently, with respect to a double precision data by which the input signal #1 is set to the high rank side and the signal #2 is set to the low rank side, a code of the low rank side is made to coincide with a code of the high rank side, processing of carrying-up and carrying-down is executed, and it is outputted. In this case, when an output switching signal 21 is ''0'', the high rank side is outputted, and when siad signal is ''1'', the low rank side is outputted. When the low rank side is being outputted, an input register 1 does not latch the input signal 11 but generates a busy signal 23, and makes an input wait. |
