| 摘要 |
PURPOSE:To realize a high speed access by two arithmetic processing devices, by executing the access again to the same address of an RAM independently from the other arithmetic processing device when one arithmetic processing device obtains a detecting output, and also resetting a detecting circuit. CONSTITUTION:When an MPU1 executes access to an RAM3, a decoder 9 detects an address signal outputted through a bus AB1 from the MPU1, and its detecting output CS1 switches bus selecting circuits 11, 12 to AB1, DB1. This operation is executed by having no relation at all with an operation of MP2, and when the MP2 executes access in the next time, the circuits 11, 12 are switched to the side of the buses AB1, AB2, respectively. In this case, when the RAM3 is subjected to access almost simultaneously by the MPUs 1, 2, an output (s) of an FF14 set by an output of an AND circuit 13 is inputted to the MPU2. As a result, the MPU2 executes access again to the same address of the RAM3, and thereafter, the FF14 is reset by a signal (r). |
