| 摘要 |
PURPOSE:To prevent extraction of a wrong clock due to a dropout, by holding the time constant of a PLL (phase locked loop) circuit at a prescribed value when a dropout is produced. CONSTITUTION:A switch SW is closed in a normal reproduction time, and a PLL circuit responds to an input signal with a normal time constant which is decided by a resistance R and the 1st capacitor C1 and can extract a correct clock. If a dropout is generated, the SW is opened and the loop of the PLL circuit is opened. In this case, the 2nd capacitor C2 is charged with the electric charge equivalent to the output of the 1st operational amplifier 5 which is obtained before generation of the dropout. Therefore, the both-terminal voltage of the C2 is delivered to an output terminal B to actuate a voltage control oscillator 3. Thus it is possible to prevent generation of a clock which is extremely erroneous even after generation of a dropout. This device can prevent extraction of a wrong clock due to a dropout. |
