发明名称 |
Bus control method. |
摘要 |
<p>In a multiprocessor system buses each coupling a pair of processors (CPU) are serially arranged rectilinearly into a cluster bus arranged in one direction. All of these cluster buses are arranged in a plurality of directions (x, y, z) as a lattice pattern when viewed in plan.
<??>Each of the processors (CPU) supplies the respective cluster buses with send requests and priority processing level signals and receives a receipt acknowledge signal from another processor on the same cluster bus, thereby to occupy said cluster bus so as to transfer data to the other processor on the cluster bus. </p> |
申请公布号 |
EP0103803(A2) |
申请公布日期 |
1984.03.28 |
申请号 |
EP19830108742 |
申请日期 |
1983.09.05 |
申请人 |
HITACHI, LTD. |
发明人 |
YABUSHITA, MASAHARU;NOHMI, MAKOTO;FUJIKURA, NOBUYUKI;MIYAMOTO, SHOJI;IHARA, HIROKAZU |
分类号 |
G06F13/38;G06F13/36;G06F13/378;G06F13/40;G06F15/173;G06F15/80;(IPC1-7):06F15/16 |
主分类号 |
G06F13/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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