| 摘要 |
PURPOSE:To prevent the operating efficiency of a processor from being decreased, by applying a clock signal with changed phase at each processor and switching a system bus of each processor with the clock signal so as to access respectively a common memory. CONSTITUTION:An MPU clock signal generating circuit 3 applies the clock signal directly to an MPU2 and to an MPU1 via a phase inverting circuit 4. Thus, since an address switching circuit 5 and a data switching circuit 9 switch address buses 11, 21 and data buses 12, 22 in the MPU1 and MPU2 and apply the signal to the common memory 8, the MPU1 can access the common memory 8 at a half period of the clock signal and the MPU2 can access the memory at the remaining half period. Thus, when one MPU accesses the common memory 8, the other MPU is at an idle time and both the MPUs can access the common memory 8 independently. |
