| 摘要 |
PURPOSE:To decide the entry of a TLB having a prescribed real address in high speed without searching all columns of TLB (Translation Lockaside Buffer) by IPTE (Invalidate Page Table Entry) instruction and SSK (Set Storage Key) instruction. CONSTITUTION:An address reverse conversion buffer 31(RTLB) storing a logical address corresponding to the real address is provided. When a new entry is registered in the TLB4, the location of the entry of the RTLB31 is decided with a bit 11-19 of the real address. When the control bit C34 of the entry is ''00'', a column address of the TLB4 is inputted to an LLA32, and ''10'' is written in the C34. As a result, the LLA32 designated with an RA9 designates the entry having the RA9 and one link is established between the entries of the TLB4 and the RTLB31. Thus, when the real address is inputted to the RAR 22 with the IPTE instruction, the corresponding entry of the RTLB31 is read out in registers 42, 43, 44, and the output of the register 44 is decoded at the control circuit 45. |
