| 摘要 |
<p>PURPOSE:To reduce the number of IGFETs, by forming only one of a multi- input circuit having many IGFETs to several word line outputs. CONSTITUTION:Since a write signal PG is at a potential of the readout power supply VCC, a potential of readout power supply voltage VCC and a write power supply voltage VPP are set to the same potential as the readout power supply voltage VCC at readout, a depletion M8 is turned on at the readout at all times and the potential of a word line WL is a ground potential being the same potential as that of an output point 2. The time when the potential of the wordline WL is discharged from logical ''1'' to logical ''0'' depends on a conductance gm of IGFETs M6, M8 and a load capacitance C1. When the potential of the word line WL is decided to logical ''0'', the IGFETM9 is turned on and an IGFETM10 is turned off, the potential at an output point 3 goes to logical ''1'', an IGFETM11 is turned off and a current from the write power supply voltage VPP to the word line WL is interrupted. Since the output at an output point 1 is separated into two with the address input signal, 2-NAND circuit of address input signals A1, A2 is halved to the word line output number.</p> |
