| 摘要 |
Operating at real-time data rates, hardware logic networks (FIGS. 3-6) receive onto a data-channel array (390 in FIG. 3) a set of unordered input data values and iteratively pair-wise transpose the set members until their positional order on the array coincides with the order the members would assume if their magnitudes were arranged according to sequential ordinal rank. Pair-wise comparisons between the data values themselves provide the basis for the mechanized pair-wise transposition schemes. Within each network, a key building block for performing both the pair comparisons and member transpositions is a Number Pair Orderer (NPO) (FIG. 2). Each NPO compares (210) two data elements and passes the smaller to one of its outputs (240), while passing the larger to the other of its outputs (260). Individual NPO's are arranged into two groups (311-315 and 321-325), each of which operates iteratively upon pairs of substantially all of the data values. The data-channel array, mechanized in a recirculatory configuration, carries the data back and forth between the two NPO groups. By making the pairs ordered by one NPO group mutually offset from the pairs ordered by the other group, a pair-to-pair transfer of unordered data elements to array positions beyond adjacent channels is accomplished. The recirculatory pair-wise ordering action is complete when the data has passed through the alternate NPO groups a sufficient number of times to enable a maximally-unordered set to be transposed into proper sequence. The networks become real-time median filters when configured to receive an odd number R of inputs and the ((R+1)/2)nd-largest member of the final ordered set is selected as the overall network output.
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