KALKYLATOR FOR ATT ALSTRA ETT M+N BITARS ADRESSORD AV TVA M BITARS DATAORD OCH FOR ATT OMVANDLA ETT M+N BITARS ADRESSORD TILL M BITARS DATAORD

摘要

A processor is disclosed having improved circuitry for (1) generating m+n-bit address words from n-bit data words and (2) converting m+n-bit address words back into data words having an n-bit format. The processor includes a first arithmetic unit (AMU) that is n bits wide and which receives n-bit words from a data bus. The processor further includes a second AMU that is m bits wide and which is connected to receive the m least significant bits of an n-bit word stored in the first AMU. An m+n-bit address word is formed by (1) applying a first n-bit word from a system data bus to the first AMU with the m most significant bits of the address word to be formed being contained in the m least significant bit positions of the first word, (2) transferring the m least significant bits from the first AMU to the second AMU and concurrently applying from the data bus to the first AMU a second n-bit word representing the n least significant bits of the address word, and (3) concurrently reading out both AMUs to apply an m+n-bit address word to a system address bus. This procedure is reversed to convert an m+n-bit address word into n-bit data words.