| 摘要 |
PURPOSE:To reduce wiring resistance by a method wherein a power source line and a load resistor are arranged in an array of memory cells, and then the maximum value of the length of a data line from a point of the connection of the load resistor to a point of the connection of the memory cell is reduced. CONSTITUTION:Each of load resistors R11, R12-Rm1, Rm2 is connected to each of the data lines di at the center of the memory cell array CA, i.e., the position for nearly equally dividing n-pieces of memory cells Mi,k connected in common to each of the data lines di into subgroup (the medium point of the data lines di). The power source line VDD is also arranged in the direction rectangular to the data lines di at the center of the memory cell array CA and then connected in common to the load resistors R11, R12-Rm1, Rm2. As the result, the influence by the resistance of the data lines di is reduced. |
