发明名称 SHRINKING SYSTEM OF FACSIMILE PICTURE SIGNAL
摘要 PURPOSE:To prevent the deterioration in picture quality and the increase in the redundancy of picture information, by converting directly the number of bits of a picture signal for one line's share into that of a reduced size to be objective. CONSTITUTION:When the reading of an original is started at a reading circuit 1, its output is converted into a binary-coding signal at a binary-coding circuit 2 and transferred to a serial-parallel converting circuit 3. This transfer is performed with a command of a microcomputer 13 every time M1 or M2 clock pulses are generated from the 1st clock generating circuit 7, and the number of clock pulses generated at each in dication are programmed in advance in an ROM or the like in the microcomputer 13 in response to the original and shrinked size. The parallel signal of M1 or M2-bit converted in parallel at each indication from the microcomputer 13 is converted into a parallel signal of N1 or N2 bits at each bit number converting circuit 5 or 6, transmitted one after another to a parallel-series converting circuit 10, where the signal is read out serially and stored in a buffer memory 11 as a shrinked picture signal.
申请公布号 JPS5950664(A) 申请公布日期 1984.03.23
申请号 JP19820161894 申请日期 1982.09.16
申请人 SANYO DENKI KK 发明人 EMI TETSUKAZU;SUZUKI OSAMU;YAMADA YOSHINORI
分类号 H04N1/04;(IPC1-7):04N1/04 主分类号 H04N1/04
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