| 摘要 |
PURPOSE:To prevent a latch up without substantially increasing the size of a chip by a method wherein a well layer is provided under an input protection resistor in a complementary MOS integrated circuit. CONSTITUTION:The first P<+> diffused layer 14 serving as an input protection diode by being connected to the input terminal for signals from the first P-well 12 wherein an N-channel MOSFET 13 is formed and from the outside is formed. The input protection resistor 17 of poly Si is formed on a substrate 11 via an insulation film 8 and then connected to the input terminal and a CMOS input circuit through metallic wirings 19a and 19b. Further, the second P-well 20 alienated from the first P-well 12 to the side is formed in the semiconductor substrate 11 under a region wherein the input protection resistor 17 is formed, and this second P-well 20 is connected to a ground point by means of a wiring 21. |
