发明名称 Circuit arrangement for processing video signals with a clamping circuit
摘要 Into the clamping circuit, a resistor acting as part of the load resistance of an amplifier stage is inserted, across which an additional voltage drop, which compensates for the reduction in the ratio between synchronisation pulse and picture signal caused by the internal impedance of the video signal source, is produced during the period of the synchronisation pulses.
申请公布号 DE3245300(C1) 申请公布日期 1984.03.22
申请号 DE19823245300 申请日期 1982.12.08
申请人 DEUTSCHE THOMSON-BRANDT GMBH, 7730 VILLINGEN-SCHWENNINGEN, DE 发明人 RUFRAY, JEAN-CLAUDE;PERY, ANTOINE, 7730 VILLINGEN-SCHWENNINGEN, DE
分类号 H04N5/06;H04N5/08;H04N5/16;H04N5/18;(IPC1-7):H04N5/18 主分类号 H04N5/06
代理机构 代理人
主权项
地址