Demodulation circuit for frequency shift signals

摘要

A demodulator circuit for recovery of an originally binary signal which has been modulated by means of frequency shift keying (FSK) has N presettable counters (302 to 305) with which the length of the intervals between two zero transitions of a zero-transition signal recovered from the received FSK signal is determined. Through storage in each counter of the two's complement of a decision threshold value interval before each counting operation, the counter reading indicates at the end of the counting operation whether the measured zero transition interval is greater or smaller than the decision threshold value. For the purposes of reducing distortion, the N counters (302 to 305) count N zero transition intervals to provide the mean value of the intervals. The counter values pass via a multiplexer (116) to a register (201) and a further register (202) connected downstream of the latter in order to determine, through comparison of two consecutive zero transition intervals by means of a delay compensation circuit (203), a delay period by which the demodulated output signal is delayed so that the latter is rendered free from distortions which occur because a change in the demodulated binary signal can take place in conjunction with a zero transition only. The additional delay corresponds to an estimation of the time at which the change in the original binary signal occurs. <IMAGE>