发明名称 ACCESS SYSTEM OF INPUT AND OUTPUT DEVICE
摘要 PURPOSE:To store more information and to allow CPU's access without increasing the number of signal lines by proving a module internally with storage holding parts more than write or read signal lines connected to a CPU. CONSTITUTION:Storage holding parts 16 and 17 are stored with write signals and also output their contents by being brought under read control. For the output, module selection signal lines 22 and 23 are used for one module. One of those two signal lines is used for a selection signal for the data writing and reading of the holding parts 16 and 17 and the other is used for the selection signal for a control part 24 which controls the storage holding parts. Consequently, the less signal lines allows an unshown CPU to access the input/output device having the holding parts A and B.
申请公布号 JPS5949622(A) 申请公布日期 1984.03.22
申请号 JP19820159486 申请日期 1982.09.16
申请人 HITACHI SEISAKUSHO KK 发明人 MATSUDA SHIYOUJI
分类号 G06F13/14;G06F13/10;G06F13/42 主分类号 G06F13/14
代理机构 代理人
主权项
地址