| 摘要 |
PURPOSE:To simplify the constitution of a circuit, to reduce the cost of the circuit and to obtain a highly accurate correction signal by using a digital circuit for a main part in addition to a multiplication type D/A converter. CONSTITUTION:A horizontal synchronizing signal is added to a PLL type frequency multiplier and a value multiplied by 2<n> times is supplied to a counter 5a. The counter 5a counts up the inputted clock signal and sends the counted result to the multiplication type D/A converter 6a. On the other hand, the output of the counter 5a is decoded by a decoding circuit 7, signals D0-D7 whose phases are delayed every mTh (m = 0-7 and Th is the period of a clock signal) from the horizontal synchronizing signal are outputted and any one of the signals D0-D7 is selected by a selection switch 8 and applied to a frequency multiplier 4a. Thus, the count starting time of the counter 5a is selected by the selection switch 8 and the fine adjustment of an upper/lower pincushion correction signal in the horizontal direction can be attained. |
