| 摘要 |
PURPOSE:To attain ease of circuit constitution and to reduce the access time, by driving dynamically a logic array with one clock pulse train. CONSTITUTION:The 1st gate circuit 1 constitutes an AND array, the 2nd gate circuit 2 constitutes an OR array, and an NAND gate circuit 3 constitutes an input control circuit. Further, the access time of a program logic array is the time until the 1st gate circuit 1 is discharged and the 2nd gate circuit 2 is precharged. When the 1st gate circuit 1 is discharged and the potential exceeds a threshold value of FETs P0-P7 of the 2nd gate circuit 2, since the 2nd gate circuit 2 is precharged immediately, the time reduced to the minimum clock time including the time when the value of an output line is stabilized. |
