发明名称 DIGITAL SCRAMBLE SYSTEM
摘要 PURPOSE:To halve the amount of memory for scramble signal, by taking a readout address as a write address of the next scramble signal. CONSTITUTION:A switching circuit 14 is switched alternately, also bring alternately picture element memories 141, 142 and field memories 151, 152 into the write state, a pattern of a scramble signal at a transmission side is changed alternately for an odd and an even number of times, the readout and write to memories at the receiving side are done alternately at a read/write control circuit 13, which takes a readout address generated at an address circuit 16 as a write address of the next scramble signal.
申请公布号 JPS5947887(A) 申请公布日期 1984.03.17
申请号 JP19820156608 申请日期 1982.09.10
申请人 HITACHI SEISAKUSHO KK 发明人 YAMAMOTO SUSUMU;NAGASHIMA TOSHIO;MOGI MINORU
分类号 H04N7/169;H04N7/16;H04N7/167;(IPC1-7):04N7/16 主分类号 H04N7/169
代理机构 代理人
主权项
地址