| 摘要 |
PURPOSE:To reduce a time required for reduction processing by synthesizing the picture element of a reduced original image directly from the picture element consisting of the original image. CONSTITUTION:A processor 8 accumulates one line of picture element consisting of the original image from a lie memory 7 at a shift register 61, and also, sets a reduction ratio (for example, 0.8) at a clock circuit 63. The clock circuit 63 extracts the picture element one by one, and transmits it to a register 62 and an OR circuit 62. The OR circuit 64 transmits the first through the third picture elements to a shift register 65 as they are, and the fourth picture element is not transmitted to the shift register 65, and in the fifth cycle, a logical sum processing between the fifth picture element transmitted from the shift register 61, and the fourth picture element transmitted from the register 62 is performed, then a new picture element being synthesized, and it is transmitted to the shift register 65. The processor 8 reads out the reduced picture element accumulated at the shift register 65, and at the line memory 7, a converted original image reduced with a reduction ratio of 0.8 in a line direction can be obtained. |
