发明名称 STEREO DEMODULATION CIRCUIT
摘要 PURPOSE:To make a multiplication circuit high accurate by using an R-2R resistance ladder D/A converter as a multiplication circuit, in an FM stereo demodulating circuit multiplying a pseudo sinusoidal wave to a composite signal. CONSTITUTION:The D/A converter 37 consists of the R-2R resistance ladder and performs multiplication to a composite signal c(t) being a reference input voltage. The composite signal c(t) is applied to the D/A converter 37 and also to a pilot signal extracting circuit 38, which extracts a pilot signal 19kHz and supplies it to a phase comparator PD40 of a PLL circuit 39. A VCO41 is locked to 608kHz with the PLL operation of the PLL circuit 39, a binary counter 42 counts 608kHz and inputs outputs Q0-Q3 to an address of an ROM45. Data D0-D7 representing each instantaneous value dividing equally one period of the sinusoidal wave into 16 are stored in 16 continuous addresses of the ROM45 and applied to a code input terminal of the D/A converter 37.
申请公布号 JPS5945732(A) 申请公布日期 1984.03.14
申请号 JP19820156382 申请日期 1982.09.08
申请人 NIPPON GAKKI SEIZO KK 发明人 KIMURA SHIGENOBU
分类号 H03D1/22;H04H40/45;H04H40/54 主分类号 H03D1/22
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