发明名称 CHROMINANCE SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To obtain the control signal of the PAL mode without increasing the number of IC pins, in the mode switching circuit of the chrominance signal processing circuit of the NTSC VTR. CONSTITUTION:A set/reset FF is provided, which inputs a set or a reset signal based on a rectangular wave pulse synchronized with the rotation of a drum and inputted from the outside of an IC. A control signal for mode switching is obtained from an output of an SR FF only at the PAL signal without providing IC pins for mode switching. That is, since a signal inputted from an input terminal 1 is as (a) having a higher minimum potential than V1 at the PAL mode, an output waveform of the 1st SW2 is as (b) and at low at all times. An output of the 2nd SW3 goes high when an input signal potential is higher than V2 and an output waveform is as (c). Thus, an output waveform at an output terminal 9 is as (e) and a high control signal is outputted. Thus, the control signal representing the PAL mode is obtained only at the PAL mode by adding four gates through the output of the SW circuit at the input terminal of the vertical synchronizing pulse synchronized with the rotation of the drum.
申请公布号 JPS5945794(A) 申请公布日期 1984.03.14
申请号 JP19820155243 申请日期 1982.09.08
申请人 HITACHI SEISAKUSHO KK 发明人 KUDOU MITSURU;NAKAGAWA HIMIO;YAMAMOTO AKIHIRO
分类号 H04N9/64;H04N9/66;H04N9/79 主分类号 H04N9/64
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