发明名称 DECODER CIRCUIT
摘要 <p>PURPOSE:To reduce the exclusive area of an EPROM element, to speed up a writing time and to obtain high reliability by converting a control signal with a VCC level into a signal with a VPP level and applying the converted signal to a selecting gate. CONSTITUTION:A write control signal C22 is converted into a signal N1 in a VPP level system through a level shifter, the signal N1 is connected to VPP at the time of writing or grounded at the time of non-writing, and a signal N2 is obtained through FETs Q25, Q26, Q28, Q29. The signal N2 is turned to VPP-alpha at the writing time or VPP at the non-writing time and then supplied to the gate of p-FET Q24 in a decoding circuit 2. If a decoder signal D21 is in the grounding level when data are to be written in a memory cell M21, a signal N4 is turned to the VCC level and a selecting gate line N3 is turned to the VPP level. When the signal D21 is turned to the VCC level, the N4 is turned to the grounding level and the N3 is also turned to the grounding level to inhibit writing.</p>
申请公布号 JPS62146486(A) 申请公布日期 1987.06.30
申请号 JP19850288707 申请日期 1985.12.20
申请人 NEC CORP 发明人 HIGUCHI MISAO
分类号 G11C11/413;G11C11/34;G11C16/06;G11C17/00;H03M7/00 主分类号 G11C11/413
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