| 摘要 |
PURPOSE:To perform smooth pipeline processing, by activating a floating-point arithmetic instruction fetched in an instruction fetch stage by a floating-point arithmetic part, and carrying out floating-point arithmetic processing in parallel to the pipeline processing. CONSTITUTION:When an instruction fetched from an instruction prefetch buffer 10 is an instruction regarding flowing-point arithmetic which requires plural machine cycles, an instruction decorder 12 generates a specific control signal CA, which is inputted to a pipeline control part 19. When the signal BUSY of the floating-point arithmetic part 18 is ''0'' (inactive), the pipeline control part 19 sends a start signal STRT to the floating-point arithmetic part 18 immediately to activated it. In this case, a floating-point register number is specified by the instruction word fetched in the 1st stage and the data is fetched to enter arithmetic processing; and the operation of a basic arithmetic part 17 and the operation of the floating-point arithmetic part 18 are performed simultaneously, so that the pipeline processing is not spoiled. |
