| 摘要 |
PURPOSE:To reduce the number of elements to improve the yield and reduce the cost by constituting an exclusive logic circuit with two inverters having the CMOS constitution, two switches, and one load element. CONSTITUTION:The output of an inverter 1 consisting of a PMOS transistor TR T1 and an NMOS TR T2 is inputted to one terminal of an NMOS TR T5 as the first switch 3 and the gate of an NMOS TR T6 as the second switch 4. The output of the second inverter 2 is inputted to one terminal of the TR T6 as the switch 4 and the gate of the TR T5 as the switch 3. A supply power VDD is inputted to one terminal of a PMOS TR T7 as a load element 5, and outputs of TRs T5 and T6 are inputted to the other terminal, and a timing signal phi is inputted to its gate. The potential of an output terminal Y is equal to that of a power source VSS if one of input signals A and B is logical '1' and the other is logical '0', but otherwise, the potential of the terminal Y is equal to that of the power source VDD. Thus, exclusive logic is attained. |
