| 摘要 |
PURPOSE:To make it possible to provide a large current, high withstand voltage, and high power, by guiding carrier flows to a region, whichis in parallel with the surface of a substrate, and to a region, which is perpendicular to the surface of the substrate, expanding the cross section of a channel per unit area, thereby making mutual conductance large. CONSTITUTION:The structure of a source and gate is basically a planar arrangement structure. Carriers flow from source regions 20 and 21 in an N region 11b between an upper gate region 19 and an embedded region 13 under the gate region 19 in the lateral direction in parallel with the surface of a substrate. The carriers, which have passed between two gates, are merged in a channel region between the gate and the gate and flow to the side of a drain region 12 in the direction perpendicular to the surface of the substrate. In this way, mutual conductance gm can be made large, low noise can be implemented, and the resistivity of the N type epitaxial layers 11a and 11b is increased. Thus the J-FET characterized by a large current, high withstand voltage, and high power can be obtained. |
