| 摘要 |
<p>PURPOSE:To accelerate line selection speed at writing/reading time by using two FETs per one memory cell for writing/reading a memory cell, eliminating a variation in a potential between the substrates of elements which forms a cell flip-flop at line selection time to reduce a parasitic capacity at line selecting time. CONSTITUTION:One ends of writing/reading field effect transistors (FET)205, 206 are connected with terminals 211, 212 of bipolar transistors 201, 202, respectively and the other ends are connected with writing/reading lines 209, 210, respectively. When address selection and writing/reading operations are executed by opening or closing the gates of writing/reading control FETs 205, 206, a parasitic capacity added to an address line 214 is only the gate capacity and the writing capacity of the FETs 205, 206 in line selection so that the parasitic capacity at line selection time becomes very small. A time required to charge/ discharge the address line 214 for the line selection is shortened in the amount of the reduced capacity, thereby shortening the line selection time.</p> |
