| 摘要 |
PURPOSE:To simplify circuit configuration, by providing the titled circuit with a signal processing circuit generating a binary code on the basis of an inputted numerical data, decoder, binary counter, multiplexer, and a monostable multivibrator, etc. CONSTITUTION:When setting switches SW0-SW3 are set up as shown in the figure, set numerical data is turned to 6911. If the numerical data to be inputted to the signal processing circuit 1 is 6601, a signal at the L level is outputted from an output terminal S1 of the decoder 6. Therefore, the multiplexer 9 generates an input, i.e., the L level signal, to a terminal X0 which corresponds to the 1st digit from a terminal Z. Therefore, the binary counter 11 is not cleared and the monostable multivibrator 7 also is not reset. When the numeral ''0'' on the 2nd digit is inputted to the decoder 6, only the output terminal S0 attains to the ''L'' level and respective outputs from the switches SW0-SW1 attain to ''H''. Consequently, the counter 11 is cleared and the monostable multivibrator 7 is reset. When the input data is 6911 and coincides with the numerical data, a matched signal with the ''H'' level is outputted from the output Q2 of the counter 11. |
