发明名称 MEMORY CONTROLLER
摘要 PURPOSE:To realize the high-speed reading and transfer regardless of the quality of media, by giving an integrated retrial process successively to the codes having errors for each designated read data length. CONSTITUTION:When a read instruction is applied from a CPU, etc. of a main system, a memory controller 2 sets the data length L to be read, the write address to the 2nd memory 3, etc. and then transmits a read command to a magnetic disk device 1. With this command data #A-#D are read out successively from the device 1 for each record, and the read error information is set to a control table 4 for each record in reponse to the error check codes added to the records #A-#D. The read data are written successively to the memory 3 regardless of the presence or absence of a read error. When the transfer is over with all data of designated length L, the controller 2 checks the table 4 and decides to complete the operation or to start a retry operation in accordance with the contents of the table 4.
申请公布号 JPS5940309(A) 申请公布日期 1984.03.06
申请号 JP19820151107 申请日期 1982.08.31
申请人 TOKYO SHIBAURA DENKI KK 发明人 SATAKE SHIGERU
分类号 G06F12/16;G06F3/06;G11B20/18 主分类号 G06F12/16
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