| 摘要 |
PURPOSE:To synchronize an internal synchronizing signal to an external synchronizing signal, by outputting two gate signals in response to a phase difference of an internal vertical synchronizing signal and an external vertical synchronizing signal based on the timing of the internal vertical synchronizing signal so as to stop the count of a counter generating the internal synchronizing signal. CONSTITUTION:A D type flip-flop 5 generates the 1st gate signal which goes to low level during the phase shift between the internal horizontal synchronizing signal and the external horizontal synchronizing signal. A dot counter 12 stops count of a clock pulse outputted from an oscillating circuit 11 while the 1st gate signal is at low level. When the period is the vertical synchronizing period, a Q output of the D type flip-flop 4 goes to high level and generates the 2nd gate signal which goes to low level during the phase between the internal vertical synchronizing signal and the external vertical synchronizing signal is shifted. Further, the dot counter 12 stops the count of the clock pulse from the oscillating curcuit 11 while the 2nd gate signal goes to low level, and a CRT controller 13 generates the internal vertical synchronizing signal synchronized with the external vertical synchronizing signal. |
