Data processing system having interlinked slow and fast memory means

摘要

A data processing system having a large slow main memory and having a small fast memory is disclosed with means for allowing slow memory calls to fast memory routines and means for allowing returns from programs executing in the fast memory so as to return to program execution in the slow main memory. Also disclosed is circuitry for selectively deactivating the main memory and for selectively activating the fast memory responsive to particular ones of data signals output from the main memory, and means for selectively deactivating the fast memory and for selectively deactivating the main memory responsive to predefined ones of data signals output from the fast memory, thereby allowing program calls embedded in the slow main memory to transfer execution control to the fast memory, and providing retransfer of execution control from the fast memory to the slow main memory in response to a RETURN code embedded in the fast memory. Thus, memory size and speeds may be selectively ratioed to obtain higher overall data processing system throughput.