| 摘要 |
PURPOSE:To improve the economical performance of an asynchronous data line exchange, by dividing plural code transmitting and receiving circuits into groups, and frequency-dividing the common code transmitting and receiving clock into a common block in the group and a clock for connecting line. CONSTITUTION:m-Set of circuits 1 are sectioned into k-set groups 61-6k comprising m1-mk-set of the circuit 1, in the asynchronous data line exchange connected to n-set of lines 4 different in transmission speed and provided with the m-set of code transmission and receiving circuits 1 transmitting/receiving the code having a transmission speed corresponding to the line. The code transmission/receiving circuit 1 in each group is connected to the line of a part of transmission speed. Each group is provided respectively with a group clock forming circuit 7, which frequency-divides the common clock signal clk applied from a main control section 3, forms group clock signals gc1-gck possible for forming the clock of the line 4 to which the circuit 1 in the concerned group is connected and applies the signals to the circuit 1 in the group. A clock forming section of the circuit 1 frequency-divides the group clock signal and forms the code transmission/receiving clock signal of the line 4 being the objective to connection. |
