发明名称 |
METHOD AND DEVICE FOR CORRECTING STEADY-STATE PHASE ERROR |
摘要 |
PURPOSE:To correct a DC phase error accurately and stably without malfunctions due to a stationary phase fluctuation and a sporadic disturbing input, by smoothing a phase error output to detect the DC phase error. CONSTITUTION:A phase comparator 28 outputs a digital signal (a binary bit signal train) corresponding to the phase difference between two input pulses (a reference pulse and a feedback phase control pulse). A latch output C of the phase comparator 28 has only DC components extracted by a digital low-pass filter (LPF) 26. The output of this LPF26 is connected to a preset circuit 32 of a speed control circuit 13, and a preset value P0 of a detecting counter 23 is changed in accordance with the change of the output of the LPF26. A preset value of a detecting counter 33 of the speed control circuit 13 is changed to change a speed control output J, thus correcting the steady-state phase error. |
申请公布号 |
JPS5938804(A) |
申请公布日期 |
1984.03.02 |
申请号 |
JP19820149303 |
申请日期 |
1982.08.30 |
申请人 |
HITACHI SEISAKUSHO KK |
发明人 |
KOBORI YASUNORI;OKAMOTO CHIKAYUKI;NISHIJIMA HIDEO;FUKUSHIMA ISAO;GOTOU KATSUHIKO;ICHIMURA SHINYA;OIKAWA TADAYOSHI;KAWABATA HIROMI |
分类号 |
G11B15/467;G05B11/36;H02P23/00 |
主分类号 |
G11B15/467 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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