发明名称 SYSTEM FOR FABRICATING TEST PATTERN
摘要 PURPOSE:To fabricate a test pattern required in testing the function of IC in good efficiency without performing manual work, by mounting a means for applying input selecting control (DRE) data and comparing-selecting control data (CPE) in the input and output common terminal of a master IC. CONSTITUTION:A CPE signal and a DRE signal are obtained from an address latch control signal (ALE), a memory laed control signal (MRD), an I/O lead control signal (IORD), a memory write control signal (MWR) and an I/O lead control signal (IOWR) generated and used in peripheral circuits of a microprocessor (UPU) 11 and/or a master IC 12a by a control data write-in circuit 152 to be stored as control data corresponding to the partial data pattern memory 154a of a test pattern memory region 15b and a test pattern with the CPE and the DRE signals can be obtained in the region 15b without performing manufal work. The test pattern is transmitted to a test pattern memory region 25b and the functional test of an IC(DUT)12b being an object to be tested is performed.
申请公布号 JPS5938671(A) 申请公布日期 1984.03.02
申请号 JP19820148939 申请日期 1982.08.27
申请人 FUJITSU KK 发明人 HAYASHI TOSHINARI
分类号 G01R31/28;G01R31/3183 主分类号 G01R31/28
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