| 摘要 |
<p>A sensing circuit for determining the amplitude of an unknown impedance (26) by comparing the voltage levels generated in a succession of current mirror circuits (21). As described, the sensing circuit is connected to a ROM array including FET devices (26) having channel structures selected from 2n possible different channel structures, corresponding to 2n possible impedances, to represent n different bits of data per ROM cell. When addressed, the selected ROM FET (26) is coupled to a current mirror reference FET, whose commonly connected gate and drain electrodes are further coupled to a succession of 2n-1 current mirror FETs (29, 31, 32). Each of the current mirror FETs (29, 31, 32) is connected in conductive series with an incrementally different impedance (37, 38, 39), the value of each impedance lying substantially midway between the 2n potential impedances possible in the ROM cell FET (26). The voltages on the current mirror FETs (29, 31, 32) are individually compared to the voltage on the current mirror reference FET (28) to generate a digital format representation of the relative magnitudes, such representation being decoded in a logic circuit (24) to provide n data bits. </p> |
